1. Field of the Invention
This invention relates to liquid crystal displays (LCD), and more particularly, to a digital LCD driving circuit for driving an LCD to display video images. In practice, the LCD driving circuit of the invention can be implemented in an LSI (large scale integration) integrated circuit that processes the video signal and associated control signals in a digital manner such that the driving circuit can be operated without laborious analog adjustments and allow the displayed video image to have higher fidelity.
2. Description of Related Art
Conventional digital display systems, such as digital cameras, image telephones, video CD (compact disc) players, global positioning systems (GPS), and so on, are typically provided with a cathode ray tube television (CRT TV) in conjunction with an LCD for displaying video images. The CRT TV is a display device which is devised to process composite video signals (abbreviated as Cvideo) in compliance with standard television standards, such as the NTSC (National Television System Committee), SECAM (Sequential Chrominance And Memory), and PAL (Phase Alternation by Line) standards. A Cvideo signal is composed of a horizontal synchronizing signal (Hs), a vertical synchronizing signal (Vs), a clock signal (CLK) and the RGB signals of the video image.
FIG. 1 is a schematic block diagram of a conventional display driving circuit for driving a CRT TV and an LCD to display video images. As shown, a composite synchronizing signal generator 102 is used to combine a horizontal synchronizing signal, a vertical synchronizing signal and a clock signal CLK into a composite synchronizing signal Csync. Meanwhile, the data of a digital dot matrix (i.e., the video image to be displayed on the CRT TV and LCD) stored in the display memory unit 103 are converted by the digital-to-analog (D/A) converter 104 into analog form and then transferred to the video encoder 105.
The video encoder 105 then processes the analog output from the D/A converter 104 and the Csync signal from the composite synchronizing signal generator 102 to thereby produce a composite video signal Cvideo. The Cvideo signal is used directly to drive the CRT TV to display the video image. It is also transferred to the LCD driving circuit (the bottom part of the circuit of FIG. 1) for further processing to obtain a suitable signal form that can be used to drive the LCD.
Alternately, the Cvideo signal can be generated through another method, for which the circuit components involved are drawn in dashed lines in FIG. 1. As shown, a digital encoder 106 can be used to process the output of the timing control circuit 101 and the digital dot matrix data stored in the display memory unit 103 to thereby generate the Cvideo signal. The Cvideo signal is used directly to drive the CRT TV and is also transferred to the LCD driving circuit for further processing to obtain a suitable signal form that can be used to drive the LCD.
The LCD includes an array of pixels, each pixel consisting of a red dot (R), a green dot (G), and a blue dot (B). These RGB dots are digitally controlled to display their associated colors in various intensity levels which are combined to show the prescribed colors of the video image. The involved techniques are conventional and not within the spirit of the invention, so description thereof will not be further detailed.
Since the LCD is different in structure and display method from the CRT TV, the analog Cvideo signal needs to be further processed before the video image can be displayed on the LCD. The LCD driving circuit is the bottom part of the circuit of FIG. 1, which includes a video decoder 111, a video amplifier 112, an analog gamma-correction circuit 113, a video inversion circuit 114, a synchronizing signal separator 120, an LCD timing control circuit 121, a phase locked loop (PLL) circuit 122, a shut-down circuit 130, a pulse width modulator (PWM) 131 and a filtering circuit 132.
As shown, in the LCD driving circuit, the Cvideo signal is first received by the video decoder 111 which then decomposes the Cvideo signal into the respective RGB signals and the composite synchronizing signal Csync. The output RGB signals are then transferred to the video amplifier 112, while the output Csync signal is transferred to the synchronizing signal separator 120.
The video amplifier 112 amplifies the RGB signals to a suitable level and then transfers the amplified RGB signals to the analog gamma-correction circuit 113 for gamma correction of the RGB signals. Gamma correction is a conventional technique for adjusting the intensity and color quality of RGB signals. It is well known to those skilled in the art so description thereof will not be further detailed. The output of the analog gamma-correction circuit 113 is then transferred to the video inversion circuit 114 for selective polarity inversion of the lines in the video signal. The polarity inversion process is performed in such a manner that neighboring lines in the video signal are designated with the opposite polarities; for instance, the odd-numbered line (i.e., the 1st, the 3rd, the 5th, . . . lines) are positively polarized, while the even numbered line (i.e., the 2nd, the 4th, the 6th, . . . lines) are negatively polarized. The technique involved for such inversion is also a conventional technique so description thereof will not be further detailed.
Meanwhile, the output Csync signal from the video decoder 111 is processed by the synchronizing signal separator 120 which decomposes the Csync signal into the original horizontal synchronizing signal Hs and the vertical synchronizing signal Vs. The horizontal synchronizing signal Hs is then transferred to both the LCD timing control circuit 121 and the PLL circuit 122. The output of the PLL circuit 122 in response to the input horizontal synchronizing signal Hs is conventionally called a pixel clock signal (abbreviated as P-CLK). The LCD timing control circuit 121 takes the vertical synchronizing signal Vs, the horizontal synchronizing signal Hs and the P-CLK signal as inputs, and then processes these signals to obtain the various video control signals required to drive the LCD to display the video image.
Moreover, since the LCD includes a positive plate and a negative plate with different types of transistors, two different DC voltages are required to drive the LCD. These DC voltages are produced by the PWM circuit 131 and the filtering circuit 132. The technique involved for supplying these two DC voltages by the PWM circuit 131 and filtering circuit 132 is also conventional and not within the spirit of the invention, so description thereof will not be further detailed.
The LCD receives the output of the video inversion circuit 114, the output of the LCD timing control circuit 121, the output P-CLK signal from the PLL circuit 122 and the output of the PWM circuit 131. These signals, in cooperation, drive the LCD to display the video image.
When the LCD is not in active use, i.e., no video signal is received, it can be shut down by the shutdown circuit 130. This provision allows the display system to save power consumption when no video image is being displayed on the LCD.
The foregoing conventional LCD driving circuit, however, has several draw-backs.
(1) First, the display of the digital dot-matrix data originally stored in the display memory unit 103 suffers from a reduced fidelity when being displayed on the LCD since these data are first processed into analog form so as to be displayable on the CRT TV and then processed in a reverse manner into digital form so as to be subsequently displayable on the LCD. The fidelity of the displayed image on the LCD is therefore considerably degraded.
(2) Second, the LCD driving circuit used to drive the LCD requires the use of quite a large number of circuit components, which cause the manufacturing cost of the LCD driving circuit to be considerably high.
(3) Third, since a large number of circuit components are required, the circuit layout space on the integrated circuit is correspondingly large, causing the integrated circuit to be less compact in size.
(4) Fourth, since a large number of circuit components are required, power consumption by the LCD driving circuit will be large, which makes the utilization of the display system less cost-effective.
(5) Fifth, since the Cvideo signal from the CRT TV driving circuit needs to be further processed so as to be displayable on the LCD, the LCD driving circuit requires the use of a large number of circuit components to process the Cvideo signal and these circuit components, such as the voltage control oscillator (VCO) in the PLL circuit and the video decoder, require various adjustments before the LCD driving circuit can be operable. These requirements considerably increase the manufacturing cost of the LCD driving circuit.
(6) Sixth, the analog gamma-correction circuit 113 is at most capable of making two- or three-stage linear gamma correction on the video signal, which still does not allow the corrected video signal to be displayed with the optimal fidelity.